1. Field of the Invention
Embodiments herein present a device, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor.
2. Description of the Related Art
For heterojunction bipolar transistors (HBTs) with a blanket silicon germanium (SiGe) layer, protecting the low temperature epitaxy (LTE) layer from reactive ion etching (RIE) is necessary to control vertical doping profile of the intrinsic part of the device. One approach is to use an etch stop layer on which an emitter opening land upon. This leads to a non-self-aligned emitter/extrinsic-base.
Another approach uses a sacrificial pedestal to define the extrinsic-base. The sacrificial pedestal is later removed to be replaced by the emitter poly. This approach is self-aligned but the final emitter dimension is determined by several process steps (pedestal, spacers, gap created by the removal of the sacrificial pedestal, a second set of spacers) which makes control and scaling of the emitter difficult.
To reduce base resistance, it is advantageous to silicide the extrinsic-base up to the spacer separating the emitter to the extrinsic-base. The resulting emitter plug is of minimum dimension and is difficult to contact by metallization without creating shorts between the emitter contact and the near-by extrinsic-base.